Sayooj S

SAYOOJ S

Available for opportunities

About

B.Tech student in Electronics and Communication Engineering with specialization in VLSI. Passionate about CPU microarchitecture, performance verification, and RTL design.

Seeking to apply skills in performance analysis, infrastructure development, and post-silicon validation in challenging hardware verification roles.

Skills

Languages

  • Python
  • Perl
  • C / C++
  • Verilog / SystemVerilog
  • Shell Script
  • Java

Tools & Platforms

  • Xilinx Vivado
  • Cadence Virtuoso
  • Git
  • Linux/Unix
  • ESP32
  • OpenCV

Core Concepts

  • CPU Microarchitecture
  • RTL Design
  • Performance Verification
  • FPGA Flows
  • Log Triage & Automation
  • Functional Coverage
  • Assertions

Projects

CPU Performance Verification & Automation

Python, Perl

Developed Python-based CPU Log Parser to parse execution logs, count instructions, detect pipeline stalls, and generate detailed execution reports. Engineered a CPU Performance Analyzer to compute key microarchitectural metrics including CPI, IPC, and execution time from simulation logs.

Mini RISC-V Processor (5-Stage Pipeline)

SystemVerilog, Vivado

Designing a pipelined RISC-V CPU core with stages: IF, ID, EX, MEM, and WB. Applying deep knowledge of CPU microarchitecture, pipeline hazards, and digital logic design to implement a functional processor.

AMBA APB Memory Interface

SystemVerilog

Implemented an AMBA APB protocol-compliant memory interface from scratch. Developed a random testbench and achieved high functional coverage to ensure design correctness and robustness.

SRAM Design & Verification

SystemVerilog

Designed and verified a synchronous SRAM module using SystemVerilog. Created a random constrained testbench and used assertions for verification, showcasing skills in modern verification methodologies.

8-bit ALU Design

Verilog, Vivado

Designed a synthesizable 8-bit Arithmetic Logic Unit supporting a range of arithmetic and logical operations, demonstrating fundamentals of RTL design.

Drowsiness Detection System

ESP32-CAM, OpenCV, Python

Developed a real-time system using embedded hardware and computer vision to detect driver fatigue, integrating hardware and software for functional validation.

YOLO-based Object Detection

Python, OpenCV, YOLO

Implemented lightweight edge AI vision for object detection tasks using YOLO algorithm and OpenCV.

Education

B.Tech – Electronics & Communication Engineering (VLSI Specialization)

KL University, Hyderabad 2023 – 2027
CGPA: 9.35

Higher Secondary (Class XII)

GSPS Thengana, Kerala 2023
CGPA: 9.3

Secondary (Class X)

Kendriya Vidyalaya Adoor 2021
CGPA: 9.5

Contact

📍 Hyderabad, India

Open for opportunities in Hardware Verification, RTL Design, and VLSI.