B.Tech student in Electronics and Communication Engineering with specialization in VLSI. Passionate about CPU microarchitecture, performance verification, and RTL design.
Seeking to apply skills in performance analysis, infrastructure development, and post-silicon validation in challenging hardware verification roles.
Developed Python-based CPU Log Parser to parse execution logs, count instructions, detect pipeline stalls, and generate detailed execution reports. Engineered a CPU Performance Analyzer to compute key microarchitectural metrics including CPI, IPC, and execution time from simulation logs.
Designing a pipelined RISC-V CPU core with stages: IF, ID, EX, MEM, and WB. Applying deep knowledge of CPU microarchitecture, pipeline hazards, and digital logic design to implement a functional processor.
Implemented an AMBA APB protocol-compliant memory interface from scratch. Developed a random testbench and achieved high functional coverage to ensure design correctness and robustness.
Designed and verified a synchronous SRAM module using SystemVerilog. Created a random constrained testbench and used assertions for verification, showcasing skills in modern verification methodologies.
Designed a synthesizable 8-bit Arithmetic Logic Unit supporting a range of arithmetic and logical operations, demonstrating fundamentals of RTL design.
Developed a real-time system using embedded hardware and computer vision to detect driver fatigue, integrating hardware and software for functional validation.
Implemented lightweight edge AI vision for object detection tasks using YOLO algorithm and OpenCV.
📍 Hyderabad, India
Open for opportunities in Hardware Verification, RTL Design, and VLSI.